Időpont: 2024. február 19.

Szervező: Dr. Nagy Zoltán, elérhetősége:

  • 09:00 – Dr. Nagy Zoltán: Bevezető 
  • 09:10 – Prof. Szolgay PéterFrom Cellular Neural Networks to  many-core digital architectures 
    • Traditionally our interest is rooted in Cellular Neural Network paradigm where the processing is done on analog computing units arranged in a two dimensonal grid and the processing elements are interconnected within a finite neighbourhood. Many-core hetrogenious architectures with low power, low dissipation, parallel operation are analysed to solve  complex computational problems. 
  • 09:30 – David Marcu (Zoom): An overview of methods for mitigating catastrophic forgetting in deep learning networks 
  • 09:50 – Florin Scurt (Zoom): The influence of sensor placement on detection capability of autonomous vehicles 
  • 10:10 – Dr. Nagy ZoltánIntroduction to RISC-V ISA 
    • The RISC-V open source instruction set architecture (ISA) is gaining more and more importance in academic and industrial applications. The open-source specification enables the creation of custom hardware implementations while maintaining compatibility with the existing software infrastructure (e.g. GCC toolchain). When creating the instruction set, the designers took extensibility into account from the beginning, making it easy to integrate application-specific instructions. In the presentation, the basic RISC-V instruction set and its design philosophy will be presented. 
  • 10:30 – szünet 
  • 10:50 – Kincses Zoltán (Zoom): Spatial Information Based OSort for Real-Time Spike Sorting Using FPGA 
    • The brain is one of the most complex biological systems containing quadrillions of synapses and billions of neurons. The spiking activity of the individual neurons can be separated from the acquired multi-unit activity with spike sorting methods. Processing the recorded high-dimensional neural data can take a large amount of time when performed on general-purpose computers. In my talk, an FPGA-based real-time spike sorting system is presented, which can process more than 11000 spikes/second, so it can be used during in vivo experiments for real-time spike sorting. 
  • 11:20 – Dr. Nagy ZoltánData structure for stencil computation on FPGA 
    • Stencil computation is an important operation in many applications such as image processing and simulation of physical processes. Its efficient implementation on various computing architectures is an active research area. The main focus of the research is optimizing data reuse by using on-chip buffers and utilizing spatial and temporal parallelism by using different tiling techniques. Generally, the mesh data is stored in row-major order in a single large continuous memory area which makes loading of data inefficient at the left and right boundaries of the tiles because data stored in modern DDR memories can be accessed in relatively large bursts. 
  • 11:50 – Sántha Levente Márk: Investigating Fast Multipole Method Acceleration Possibilities on Different Architectures 
    • In this presentation the desired goal is to compare the efficiency of different hardware platforms implementing Fast Multipole Method (FMM). FMM is one of the greatest algorithms of the XX. century and can be used to solve the so-called N-body problem. We also cover the brute force solutions and try to show the advantages and disadvantages of the FMM concept. One- and two-dimensional examples are examined. During the implementation we attempted to benefit from the unique properties of the hardware platforms (e.g.: several computing cores may be used). We demonstrate different implementations on PC and on Field Programmable Gate Array (FPGA) with high-level hardware synthesis and benchmark the resulting hardware in terms of speed, and power consumption.